The task of verification has become even more time consuming and more complex as well since mixed signal and analog content keeps improving in modern SoC designs. There are a number of power domains, design size, block interfaces as well as unfamiliar hardware description languages that have contributed to the difficulties of engineer who's assigned for the verification process.
As a matter of fact, the realm of digital verification has gained significant development with different methodologies to be able to tackle these issues just like assertions, model abstraction and coverage driven test benches. Whether you believe it or not, the verification for the analog and mixed signal or (AMS) systems are mostly relied on manual approaches. The white paper is discussing how the digital techniques may be applied to be able to have an in-depth verification of most complex mixed signal designs in an efficient and timely manner. Please click here for more information.
And even though mixed signal SOC being a commonplace, there's still no standard methodology applied in the verification of these chips. As a result, this causes an ever-growing percentage of design respins mainly because of the increased in analog content. Take a look at this interesting article about lasers at http://www.huffingtonpost.com/2013/10/24/nasa-lasers-moon-new-record-data-transfer_n_4151765.html. Designers ought to sign off on tape outs as confidently and quickly as possible. However, the verification of digital blocks and analogs are executed by 2 separate and disjointed processes.
Either by writing simple HDL models of analog blocks and simulating the system entire in digital simulation tools or, simulating the entire chip at transistor level by using a certain tool is the most typical approach for the verification of mixed signal blocks.
Both of the said solutions of course have their respective advantages and disadvantages. Although there are considerable improvements in technology when simulating the entire chip at a transistor level using a particular tool, the process of simulations are somewhat slow in comparison to gate level digital simulation. Because of this, achieving comprehensive functional coverage is not always possible. It is very efficient in terms of its runtime by being able to produce digital models in describing the analog functionality. However, the models are quite difficult to correlate to analog implementation lacking of the required fidelity. Thus, it has been a common scenario to overlook bugs. Check out these precision TEC controllers.
As a matter of fact, it have opened up new possibilities of taking full advantage of both worlds as Custom simulation has this ability of co-simulating with Synopsys' VCS digital simulator. Believe it or not, the utilization of mixed signal approach has lead to opening a number of philosophies and techniques that are common in digital world, which can be applied to the verification of mixed signal systems.
As a matter of fact, the realm of digital verification has gained significant development with different methodologies to be able to tackle these issues just like assertions, model abstraction and coverage driven test benches. Whether you believe it or not, the verification for the analog and mixed signal or (AMS) systems are mostly relied on manual approaches. The white paper is discussing how the digital techniques may be applied to be able to have an in-depth verification of most complex mixed signal designs in an efficient and timely manner. Please click here for more information.
And even though mixed signal SOC being a commonplace, there's still no standard methodology applied in the verification of these chips. As a result, this causes an ever-growing percentage of design respins mainly because of the increased in analog content. Take a look at this interesting article about lasers at http://www.huffingtonpost.com/2013/10/24/nasa-lasers-moon-new-record-data-transfer_n_4151765.html. Designers ought to sign off on tape outs as confidently and quickly as possible. However, the verification of digital blocks and analogs are executed by 2 separate and disjointed processes.
Either by writing simple HDL models of analog blocks and simulating the system entire in digital simulation tools or, simulating the entire chip at transistor level by using a certain tool is the most typical approach for the verification of mixed signal blocks.
Both of the said solutions of course have their respective advantages and disadvantages. Although there are considerable improvements in technology when simulating the entire chip at a transistor level using a particular tool, the process of simulations are somewhat slow in comparison to gate level digital simulation. Because of this, achieving comprehensive functional coverage is not always possible. It is very efficient in terms of its runtime by being able to produce digital models in describing the analog functionality. However, the models are quite difficult to correlate to analog implementation lacking of the required fidelity. Thus, it has been a common scenario to overlook bugs. Check out these precision TEC controllers.
As a matter of fact, it have opened up new possibilities of taking full advantage of both worlds as Custom simulation has this ability of co-simulating with Synopsys' VCS digital simulator. Believe it or not, the utilization of mixed signal approach has lead to opening a number of philosophies and techniques that are common in digital world, which can be applied to the verification of mixed signal systems.